Intel introduces high-performance chip family Xeon Phi

Intel introduces high-performance chip family Xeon Phi

PanARMENIAN.Net - Intel on Monday, June 18 introduced a high-performance chip family called Xeon Phi, which provides a stepping stone for the company to reach the milestone of creating an exaflop computer by 2018, InfoWorld reports.

A chip code-named Knights Corner will be the first Xeon Phi processor released by Intel later this year. Targeted at supercomputers, Knights Corner will have more than 50 cores and deliver power consumption breakthroughs while scaling performance when conducting complex calculations, said Rajeeb Hazra, vice president of the Intel Architecture Group and general manager of technical computing.

The next big milestone for supercomputers is to reach exaflop performance, which would be about 100 times as fast as today's fastest computers. Chip makers Intel and Nvidia are in a race to claim the lead in exaflop computing by building specialized chips that can execute more calculations per second while keeping power consumption in check. Supercomputers are now harnessing the parallel-processing capabilities of these graphics processors and chips like Phi to perform complex calculations tied to scientific and math research.

The Xeon Phi chips will be part of the Xeon server chip family, which is used in a majority of industry-standard servers to process cloud and database applications. Intel has acquired a host of fabric technologies from companies like Qlogic and Cray to provide the bandwidth to shuttle data in supercomputers.

Intel calls the first Xeon Phi chip a co-processor, as it needs a server CPU such as the Xeon E5 to work on computer systems. The Phi chip will be used in a supercomputer called Stampede, which could go live as early as the end of this year at the Texas Advanced Computing Center at the University of Texas.

Intel has been talking about the Knights Corner chip - then called the MIC (many integrated cores) chip - since 2010. The chip came out of Intel's research and development laboratory, and was designed with size, complexity and power consumption in mind.

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